1. Field of the Invention
The present invention relates to electro-static discharge (ESD) protection circuits for integrated circuits, and more particularly ESD protection of an integrated circuit's output MOS transistors.
2. Background Information
As integrated circuits (ICs), especially CMOS circuits, are reduced in size into the sub-micron range with ever thinner oxide layers, shallower junctions, more lightly doped structures, and silicided diffusions, the structures become ever more susceptible to ESD induced failures. Human and/or mechanical handling produces static charges that can and do cause destructive failure in such ICs. The components most at risk of such a failure are those that are electrically connected to output terminals or pads leading off the printed circuit board that carry the components. It has been found that human body ESD stress will damage an output NMOS even though there is a primary ESD protection cell located on the NMOS.
ESD voltage stress, event, ESD voltage spike or voltage stress is understood in the art as being interchangeable.
Generally, ESD voltage stresses produce voltages that permanently damage thin oxide insulting layers and/or uneven current densities that damage junctions and/or diffusion profiles in small areas. These mechanisms have been well documented in the art. For example, see “Achieving Uniform NMOS Device Power Distribution for Sub-micron ESD Reliability,” by C. Duvvury, C. Diaz, and T. Haddock, in IEDM Technical Digest, 1992.
Prior art ESD protect circuits include series resistors, filter capacitors, clamp diodes and Zeners or other such breakdown devices employed at the terminals to limit the effect of the ESD event. These protection techniques are designed, inter alia, with marginal success to trigger at ESD voltages higher than the typical operating voltages of the product itself, so that the ESD protection does not interfere with the typical product functional operation.
The problem is that an ESD event at an output, where the output has an NMOS to Vss, or ground and a PMOS to a power rail, Vdd, couples through the PMOS capacitor to the Vdd rail and through the logic circuitry involved to turn on the NMOS. The NMOS discharges the ESD event and prevents primary ESD protection devices from operating fully, if at all. More troublesome is that as the NMOS is turning on, it may enter a “snap-back” condition (well known in the art) where parasitic bipolar transistors may turn on. In such conditions the output NMOS often will fail or be substantially weakened so as to exhibit increase leakage after the ESD stress is removed. Such components may fail in the field, which is worse. FIG. 1 illustrates the operation. Even with clamps 10 on the output, the NMOS N1 may turn on. The clamp 10 is shown generically. A positive going voltage spike on the OUTPUT, say by a human touching it, is coupled through the output capacitances C1 and C2 of the PMOS's P1 and P2 to the gate of N1. There is nothing to prevent N1 from turning on and reducing the voltage spike. Reducing the voltage spike may interfere with the primary ESD protection device, the clamps 10, or any protective circuits attached directly to the +Vdd line from fully activating. As discussed later, in fact, the NMOS N1 and the clamps 10 will share discharging the voltage spike, but the issue is that N1 is susceptible to failure.
U.S. Pat. No. 5,239,440 to Merrill addresses such an issue. Merrill provides a single RC detection circuit to actively turn on protective MOS switches attached to each output. On each output there is a transistor switch to Vcc and one to Vss (one to power and one to ground). Depending on the polarity of the ESD event, the proper switch is activated.
The prior art circuits have a number of limitations that are directly addressed by the present invention. Among those limitations is that the pull down NMOS on the output still may turn on, regardless of the switches or clamps on the output node. Moreover, the switches on each output provide a connection between each output (for example when the switches are not activated) that may allow transients to cause noise in adjacent output even with the low impedance Vcc or ground connections. Another significant limitation is that the two switches (as in the Merrill “clamp”) on each output occupy valuable chip area.